The Department of Commerce and the National Semiconductor Technology Center’s operator, Natcast, have unveiled the processes for selecting the first three research and development facilities that will be funded under the CHIPS and Science Act.
The National Institute of Standards and Technology said Friday an NSTC Prototyping and National Advanced Packaging Manufacturing Program—or NAPMP—Advanced Packaging Piloting Facility, an NSTC Administrative and Design Facility and an NSTC Extreme Ultraviolet Center will help address the gap between industry and research by bringing together partners across the semiconductor ecosystem.
The NSTC Administrative and Design Facility is expected to be operational in 2025 followed by the NSTC EUV Center in 2026.
Natcast and the department expect the NSTC Prototyping and NAPMP Advanced Packaging Piloting Facility to become operational in 2028.
The NSTC Prototyping and NAPMP Advanced Packaging Piloting Facility will provide NAPMP-funded researchers and NSTC members with prototyping, packaging and research capabilities to facilitate advanced packaging and semiconductor research.
The NSTC Administrative and Design Facility will host Natcast administrative functions and support various activities, including advanced semiconductor research in electronic design automation, chip and system architecture, chip design and hardware security.
The NSTC EUV Center will provide members access to EUV technologies and space to perform research efforts.
Natcast and the department will release an ecosystem questionnaire to economic development organizations across the U.S. to help identify semiconductor ecosystems that could support the NSTC Prototyping and NAPMP Advanced Packaging Piloting Facility.
The Commerce Department and Natcast will use three separate site selection processes for the facilities. For the NSTC Administrative and Design Facility, they will use a two-phase selection process: identifying semiconductor design ecosystems and determining locations and performing diligence and negotiations.
Click here to learn more about the selection processes for the three CHIPS R&D facilities.
